Accompanied with continual development of the electronic technology, various electronic products are becoming more and more versatile with overwhelmingly diversified functions. Therefore, innovated circuit designs of chips are also becoming more and more complicated in order to meet user requirements upon the electronic products.
In a conventional integrated circuit (IC) design flow, an engineering change order (ECO) is a back-end engineering change step. Supposing a logic circuit is established from a register transfer level (RTL) hardware description language (HDL), the RTL HDL is synthesized into a gate level HDL, and then converted into an optimized gate level HDL via automatic placement and routing (APR).
At the current phase, since the logic circuit has undergone synthesis and APR, all functional components included in the logic circuit are coupled to or merged with one another, or simplified, such that the logic circuit is able to pass timing constraints while also reducing its utilization area. As a result, modifications on the optimized gate level HDL of the logic circuit according to ECO become extremely challenging.
One of the greatest difficulties in ECO is that, in order to proceed with modifications on the optimized gate level HDL of the logic circuit, it is necessary to first perform a logical equivalent check between the RTL HDL and optimized gate level HDL of the logic circuit to ensure modifications made on the logic circuit are correct at both RTL HDL and optimized gate level HDL phases. More specifically, to make modifications according to ECO, it is necessary to repeatedly check between the synthesized gate level HDL and optimized gate level HDL phases and then perform detailed and complicated data import and export.
Accordingly, it is apparent that finding ECO points in the synthesized, optimized and APR gate level HDL of the logic circuit is much more difficult than finding those in the RTL HDL of the logic circuit. Such difficulties mean that a great amount time and resources are required for finding possible ECO points in the complicated APR gate level HDL of the logic circuit. Consequently, a progress of the entire IC design flow may be seriously affected to lead to delays in product manufacturing and time-to-market.
Therefore, it is an objective of the invention to provide a change point finding method and apparatus for overcoming the foregoing issues.